This really depends on the requirements of the design, but a typical thing to do is to leave enough space between the IO ring and the core for your core power rings.
You're on the right track! You definitely want enough space for your VDD and VSS ring plus the space between them (5u+5u+2.5u), but also add some space for the distance from the edge of your IO cells to the start of the pwr/gnd ring and from the other side of the pwr/gnd ring to the core, so that you don't have metal spacing violations in these areas. You could look in your LEF file for the largest spacing rule for the metals and use that value (use the spacing rule for the widest metal on the IO side, since there may be wide metal busses inside the IO).
Hope that helps,