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Partitioning the design.

gops
I know how to partition a design but I need to know about the purpose of partitioning the design. I have read that this helps in splitting the design among various layout engineers.But i don't understand how it's possible. By partitioning i think a hierarchical module i can assign the pin position and the cell density of the module . After partitioning how should i transfer the partitioned block to another layout engineer so that he could do the CTS, routing and optimization of the design? thanks gops.
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  • The "savePartition" command creates a directory structure that enables the tool to be run on each hierarchical module you elect to specify as a partition.  For example, if you do a "savePartition -dir PTN" after completing the partitioning process, the structure will look like this (for the tutorial circuit shipped with the software):

    PTN/DTMF_CHIP <- This is the top level of the design with 2 partitions hardened
    PTN/results_conv <- This is a partition
    PTN/tdsp_core <- This is a partition

    Each of these directories will contain an FE .conf file that you can use to initialize the design.  Further, all of the data needed to perform block level implementation should be present:

    results_conv.conf
    results_conv.v
    results_conv.fp
    results_conv.fp.spr
    results_conv.place.gz
    results_conv.route.gz
    results_conv.constr.pt
    results_conv.constr.warn
    lib.defs
    results_conv.mode

    I've posted a 5-minute screencast on the subject of partitioning in general here:

    /blogs/di/archive/2008/11/06/demo-partitioning-a-design-in-soc-encounter.aspx?postID=12440

    Hope this helps,
    Bob

Reply

  • The "savePartition" command creates a directory structure that enables the tool to be run on each hierarchical module you elect to specify as a partition.  For example, if you do a "savePartition -dir PTN" after completing the partitioning process, the structure will look like this (for the tutorial circuit shipped with the software):

    PTN/DTMF_CHIP <- This is the top level of the design with 2 partitions hardened
    PTN/results_conv <- This is a partition
    PTN/tdsp_core <- This is a partition

    Each of these directories will contain an FE .conf file that you can use to initialize the design.  Further, all of the data needed to perform block level implementation should be present:

    results_conv.conf
    results_conv.v
    results_conv.fp
    results_conv.fp.spr
    results_conv.place.gz
    results_conv.route.gz
    results_conv.constr.pt
    results_conv.constr.warn
    lib.defs
    results_conv.mode

    I've posted a 5-minute screencast on the subject of partitioning in general here:

    /blogs/di/archive/2008/11/06/demo-partitioning-a-design-in-soc-encounter.aspx?postID=12440

    Hope this helps,
    Bob

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