Stats

  • Locked Locked
  • Replies 13
  • Subscribers 95
  • Views 21554
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Encounter DEF file export

rayz

I am trying to export my layout from Encounter to Cadence DFII ennvironment using DEF format.  Apparently the DEF file generated by Encounter does not contain all the VIA definitions or Virtuoso has problem reading them since when the design is imported in Virtuoso some of the VIAs are missing and I see warniong message that VIA definitions are missing. Do you have any experince dealing with this issue.

Thanks

Parents
  • ScreenName

     Hi,

     Nowadays, it is difficult to explain we still use DEF/LEF format to exchane design. Most of people, especially EDA tool sellers, want we use all of their methodology (OpenAccess, GDSII, and another complicated and dark format which are not as easy as the "old fashionned" but reliable DEF....)

     I prefer, as you, these methodology (based on DEF), because it is easier to debug, net/instance names are respected, verilog and layout are well aligned along the design flow, and it's better to map RC extract, on DEF, with verilog Name etc...

     So, if you want to export Via LEF definition in your Defout with Encounter, you may switch to 1 the variable defOutLefVia   (in encounter, before defOut, you put "set defOutLefVia 1"  or through the gui, Design->Global Variables)

     You'll have the via defined as same as in the LEF file at the begining of the DEF file. A problem could appear if your technology is not aligned between Virtuoso (DFII techfile --editable --) and Encounter (LEF technology), concernig the array of Via...In case of mismatch, they will be created in the library for DefIn, as instantiated cell (and not as ViaArray generated from technology library) But you'll have your design, and their via.

    It could avoid all of workAround to preserve instance names, or net name in another format...

     BR

    Haf.

Reply
  • ScreenName

     Hi,

     Nowadays, it is difficult to explain we still use DEF/LEF format to exchane design. Most of people, especially EDA tool sellers, want we use all of their methodology (OpenAccess, GDSII, and another complicated and dark format which are not as easy as the "old fashionned" but reliable DEF....)

     I prefer, as you, these methodology (based on DEF), because it is easier to debug, net/instance names are respected, verilog and layout are well aligned along the design flow, and it's better to map RC extract, on DEF, with verilog Name etc...

     So, if you want to export Via LEF definition in your Defout with Encounter, you may switch to 1 the variable defOutLefVia   (in encounter, before defOut, you put "set defOutLefVia 1"  or through the gui, Design->Global Variables)

     You'll have the via defined as same as in the LEF file at the begining of the DEF file. A problem could appear if your technology is not aligned between Virtuoso (DFII techfile --editable --) and Encounter (LEF technology), concernig the array of Via...In case of mismatch, they will be created in the library for DefIn, as instantiated cell (and not as ViaArray generated from technology library) But you'll have your design, and their via.

    It could avoid all of workAround to preserve instance names, or net name in another format...

     BR

    Haf.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.