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Encounter SDF file for APR simulation in NC Sim

TOK47

Recently, I just convert from ASTRO to ENCOUNTER.

I am trying to setup the simulation enviroment for NC Sim y using Encounter SDF file.

But, unluckily, I faced a big problem. The setup and hold time for all my flop were screw up.

I do check my Encounter SDF file with using ETS, I din't see any time violation.

Any ideas?

Thanks.

Parents

  • After some debugging activities, I found out that there were some missing TIMINGCHECK information for flops and latches.

    In my sdf file, it just shown

     (CELL
        (CELLTYPE  "dffp_1x")
        (INSTANCE  xxxxxxx/xxxxx/xxxx/xxx
          (DELAY
            (ABSOLUTE
            (IOPATH (posedge CK) Q  (0.264::0.768) (0.287::0.853))
            (IOPATH (posedge CK) QN  (0.290::0.873) (0.271::0.799))
            )
          )
          (TIMINGCHECK
             )
      )

     So, my simulator prompt a error message on ' ) ' and stop loading the rest of the file after the error line.

    After I manually remove those error lines. My simulation looks fine for those delay between 1 signal and 1 signal.

    But, now, I notice another error. The time delay between input and output of certain logic was alway 1ns.

    Q:  1. Is this time delay information for logic cell in determine in sdf file? 

         2. Is something I missed out in my simulation setting?

    Thanks


Reply

  • After some debugging activities, I found out that there were some missing TIMINGCHECK information for flops and latches.

    In my sdf file, it just shown

     (CELL
        (CELLTYPE  "dffp_1x")
        (INSTANCE  xxxxxxx/xxxxx/xxxx/xxx
          (DELAY
            (ABSOLUTE
            (IOPATH (posedge CK) Q  (0.264::0.768) (0.287::0.853))
            (IOPATH (posedge CK) QN  (0.290::0.873) (0.271::0.799))
            )
          )
          (TIMINGCHECK
             )
      )

     So, my simulator prompt a error message on ' ) ' and stop loading the rest of the file after the error line.

    After I manually remove those error lines. My simulation looks fine for those delay between 1 signal and 1 signal.

    But, now, I notice another error. The time delay between input and output of certain logic was alway 1ns.

    Q:  1. Is this time delay information for logic cell in determine in sdf file? 

         2. Is something I missed out in my simulation setting?

    Thanks


Children
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