HELP: synthesis of a Verilog code into a matrix crossbar (running at a frequency >= 1GHz) using Encounter

 Hello,

I have a verilog code that i'm trying to synthesize using Encounter. the verilog code describes a basic 8 port matrix crossbar and I want to  sythesize this crossbar to run at frequencies greater than 1GHz. im using 90nm IBM9SF technology. I run into negative setup and hold slack values. I'm already using the following lines to have encounter correct these negative slack errors, but so far i have not been successful. Could anyone please tell me what other commands (besides the ones listed below) i can use to correct these negative slack values? thank you very much.

# This does the actual placement
placeDesign
addTieHiLo -cell "TIEHITH TIELOTH" -prefix TIE

# Optimize the placement
setOptMode -reclaimArea -highEffort -fixFanoutLoad
#setOptMode -highEffort
optDesign -preCTS

refinePlace

# Clock tree synthesis
#------------------------------------------------------------

setCTSMode \
    -topPreferredLayer 6 \
    -bottomPreferredLayer 4 \
    -noUseLibMaxFanout \
    -addClockRootProp \
    -useCTSRouteGuide

createClockTreeSpec \
    -output par.ctstch \
    -routeClkNet \
    -bufFootprint {CLKBUFX8} \
    -invFootprint {INVX8} \

specifyClockTree -clkfile par.ctstch
ckSynthesis -rguide par_clk.rguide

setOptMode -highEffort -fixFanoutLoad -fixHoldSearchRadius 100
optDesign -postCTS -hold -setup -prefix postCTS

# The clock router sometimes (incorrectly) routes M2 over pins,
# causing violations this allows those routes to be moved later
changeUseClockNetStatus -noFixedNetWires

# Save design for debugging
saveDesign postclksynth -netlist -tcon -rc

# Routing
#------------------------------------------------------------
# Deleting dummy cells
#specifyCellPad DFF* 10
deleteAllCellPad
queryPlaceDensity > postCellPadRemoval_placement_density.rpt
setDelayFootPrint INVX1
setBufFootPrint CLKBUFX1

# Wire up cells to power network
sroute -noStripes -noPadRings -jogControl { preferWithChanges differentLayer }

# Do signal routing
setNanoRouteMode -drouteFixAntenna true
setNanoRouteMode -routeInsertAntennaDiode false
setNanoRouteMode -timingEngine CTE
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeWithEco false
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeTdrEffort 10
setNanoRouteMode -routeSiEffort high
setNanoRouteMode -routeWithSiPostRouteFix false
setNanoRouteMode -drouteAutoStop true
setNanoRouteMode -routeSelectedNetOnly false
setNanoRouteMode -envNumberProcessor 1
setNanoRouteMode -droutePostRouteSwapVia true
globalDetailRoute

setOptMode -highEffort -fixHoldSearchRadius 100 -fixFanoutLoad
optDesign -postRoute -hold -prefix postroute
optDesign -postRoute -drv -setup -prefix postroute

# Add filler/feedthrough cells
addFiller -cell FILL1TH FILL4TH FILL8TH -prefix FILL

checkRoute
checkDrc