Decap cells

Hi Gopakumar

Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail.  

As already mentioned on the forum, when there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in the design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open.

One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating. I have seen designs fail because of this

Designers typically place decap cells near high activity clock buffers, but I recommend a decap optimization flow where tools study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into account to ensure resonance frequency is not hit.

Thanks

Mohammad

Hi Mohammad

Nicely explained but my query is that 

Is it preferable to connect directly power  to gate terminal ?

and could you please elaborate on how decaps have more leakage?

Thanks

vs8747

Hi Mohammad

Nicely explained but my query is that 

Is it preferable to connect directly power  to gate terminal ?

and could you please elaborate on how decaps have more leakage?

Thanks

vs8747