How to preserve logical function at hierarchical ports after some timing optimizations done with setOptMode -preserveModuleFunction false.

 Hi There,

I have an issue regarding setOptMode -preserveModuleFunction false.
I have set this option to false, so FE will do optimization disregarding if logical function changes occur at hierarchical output ports.

One example of this is splitting an inverter pair across hierarchy boundaries.

But *now*, my verification guys want me to preserve the logic function at module output ports.
I don't want to go back before any timing optimization perform all optimization again with the -preserveModuleFunction true.

Is there a way to fix it in a design after optimization have been done?

I was thinking in some script that detect some split inverter pair and change the inverters name to be inside the same module hierarchy.

Someone has faced some similar problem?

Thanks!