Stats

  • Locked Locked
  • Replies 1
  • Subscribers 91
  • Views 13131
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

DVFS

gops
I know DVFS is a method to reduce power. But if I vary (reduce) the frequency of operation keeping Voltage constant , Can i achieve dynamic power reduction comparable to DVFS .

  •  Hi gops,

     

    DVFS stands for Dynamic Voltage Frequency Scaling. What you are proposing is varying the frequency without changing the volatge.That will certainly reap you some of the rewards but full DVFS will provide you better overall performance (power, timing, and ultimately area as well) To answer your question, you certainly achieve power reduction as you suggested. However you will not be able to achieve as much power reduction (or you will give up more performance) by locking the voltage. I suggest you take a look at the Common Power Format and what it would take to use DVFS since there is a pretty well established methodology to do DVFS using CPF. If it is any help, Si2 has a pretty detailed low power design manual which you can download for free (if I am not mistaken) if you are interested.

     

    hope this helps,

    gh-

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.