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NanoRoute Ultra for structured ASIC routing?

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Hi,

In general can NanoRoute Ultra be used for structured ASIC routing? A structured ASIC would have preplaced blocks, so the routing problem is somewhat different compared to typical standard cell or block based routing situations. Can NanoRoute Ultra still be used?

Also can NanoRoute Ultra make use of preplaced buffers in the structured ASIC to improve timing of nets?

Also is it possible to specify routing architectures using NanoRoute Ultra? For example, suppose I wanted to create a routing architecture for my structured ASIC composed of a fixed pattern on metal layers 5 and 6 with customization provided by intermediate via layer 5. Can I somehow specify such a routing structure to NanoRoute Ultra and then make it work with this routing structure during routing?

If Nanoroute Ultra is not really meant for such a problem, is there any workaround that is possible?

All comments/suggestions from Cadence employees/NanoRoute Ultra users would be very helpful. Thanks greatly!


Originally posted in cdnusers.org by cdnuser78
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