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Excluded pin during CTS

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During CTS-run I've defined my clocktree as below:

AutoCTSRootPin TIMMCORE/u_core/u_coss/u_efc/u_fb_fs/f_wre_reg/Q
MaxDelay 7.0ns # set_clock_latency
MinDelay 6.7ns # default value
MaxSkew 300ps # set_clock_uncertainty
SinkMaxTran 900ps # set_clock_transition
BufMaxTran 900ps # set_clock_transition
Buffer dly1x3pdv dly2x3pdv dly2x8pdv dly3x3pdv
RouteType standard_clk
AddDriverCell cnbfx6pdv
PadBufAfterGate NO
NoGating NO
DetailReport YES
RouteClkNet YES
PostOpt YES
ExcludedPin
+ TIMMCORE/u_core/u_coss/u_efc/u_fb_fs/loc_tdo7_reg/TI
LeafPin
+ TIMMCORE/u_core/u_coss/u_efc/u_flash/WRE
END

But after CTS, the delay from the clock root to */TI
as same as the delay to the */WRE. My expecting is that the */TI pin should be excluded from the clocktree.

Ps. I'm using (cadence_fe 04.20-s315_1_USR2 )


Originally posted in cdnusers.org by DN

  • I've just found that when you define (SetDPinAsSync YES) in the CTS-configuration file then it works.

    From user guider
    SetDPinAsSync YES | NO
    Controls whether CTS automatically treats the D-pins of flip-flops as synchronous pins.

    D-pins include

    Data pins

    Enable pins

    Scan-in pins

    Scan-enable pins

    Synchronous set and reset pins

    Default: If you omit this statement, CTS treats the D-pins of flip-flops as excluded pins. That is, CTS does not treat the pins as synchronous pins.


    Originally posted in cdnusers.org by DN

  • Hi, Let me add few more comments on your topics,
    The alternative way other then adding in script file is by setting the same in CTSMode "setCTSMode -setDPinAsSync " before loading ctstch script file.

    Then this is global for all the other CTS trees.
    Its allways adviceble to set soft rule for Preferred layers like avalable top metals (M5 , M4 ) in setCTSMode command .
    like ( setCTSMode -topPreferredLayer M4  -bottomPreferredLayer M3 ) .
    BTW how was your correlation of skew and delay between clk- route only and post route phase.

    Regards,
    Mohan


    Originally posted in cdnusers.org by mohanch007

  • Hi, Let me add few more comments on your topics,
    The alternative way other then adding in script file is by setting the same in CTSMode "setCTSMode -setDPinAsSync " before loading ctstch script file.

    Then this is global for all the other CTS trees.
    Its allways adviceble to set soft rule for Preferred layers like avalable top metals (M5 , M4 ) in setCTSMode command .
    like ( setCTSMode -topPreferredLayer M4  -bottomPreferredLayer M3 ) .
    BTW how was your correlation of skew and delay between clk- route only and post route phase.

    Regards,
    Mohan


    Originally posted in cdnusers.org by mohanch007

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