Stats

  • Locked Locked
  • Replies 3
  • Subscribers 90
  • Views 15357
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Clock path crosses data path

archive

Hi,

Would like to know how the following can be handled in Encounter flow.

The data path is from a FF to another FF, and both FF are clocked by the same clock. In the data path, there is an OR gate. One of the input of the OR gate is from a clock source. The other input of the OR gate is data.

As the OR gate is part of a clock network, the placer does not optimise it. Hence, during optDesign, due to the high-fanout of the OR gate, the delay of the OR gate is 200+ns. This result in a huge violation, and the QOR become bad.

I have tried to use "setAnalysisMode noclksrcpath", but since the source of this path is data, the option does not effect.

I workaround by setting a multicycle path from these 2 FFs during physical synthesis, and then remove it before clock tree synthesis. However, is there a better solution for this type of design? Thanks.

Regards,
Eng Han


Originally posted in cdnusers.org by EngHan
Parents

  • Hello Han,

    IF the output of the OR gate is clock and not data, the placer needs to know that it is a clock gating cell. You must do two things prior to placement and optimization:

    1) specifyClockTree -clkFile clock_spec.cts
    2) setPlaceMode -clkGateAware

    This should help the placer to try and find an optimal placement for the OR gate relative to it's leaf cells.

    IF the output of the OR gate is to a data pin, it should still see the timing path and optimize it.

    Please let us know if this helps.

    Best Regards,
    Mike Jacobs
    Cadence Design Systems


    Originally posted in cdnusers.org by mikenaustin
Reply

  • Hello Han,

    IF the output of the OR gate is clock and not data, the placer needs to know that it is a clock gating cell. You must do two things prior to placement and optimization:

    1) specifyClockTree -clkFile clock_spec.cts
    2) setPlaceMode -clkGateAware

    This should help the placer to try and find an optimal placement for the OR gate relative to it's leaf cells.

    IF the output of the OR gate is to a data pin, it should still see the timing path and optimize it.

    Please let us know if this helps.

    Best Regards,
    Mike Jacobs
    Cadence Design Systems


    Originally posted in cdnusers.org by mikenaustin
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.