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  3. Clock path crosses data path

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Clock path crosses data path

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archive over 19 years ago

Hi,

Would like to know how the following can be handled in Encounter flow.

The data path is from a FF to another FF, and both FF are clocked by the same clock. In the data path, there is an OR gate. One of the input of the OR gate is from a clock source. The other input of the OR gate is data.

As the OR gate is part of a clock network, the placer does not optimise it. Hence, during optDesign, due to the high-fanout of the OR gate, the delay of the OR gate is 200+ns. This result in a huge violation, and the QOR become bad.

I have tried to use "setAnalysisMode noclksrcpath", but since the source of this path is data, the option does not effect.

I workaround by setting a multicycle path from these 2 FFs during physical synthesis, and then remove it before clock tree synthesis. However, is there a better solution for this type of design? Thanks.

Regards,
Eng Han


Originally posted in cdnusers.org by EngHan
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  • archive
    archive over 19 years ago

    Hi Mike,

    The tricky thing is that the output of the OR gate is both clock and data.

    One experienced AE advice me that the way to handle this is to use "setExcludeNet" command. I think the command is a good workaround. However, I am not using it now as the OR gate is a synthesized gate, and thus the net name will change with every new synthesized netlist. I should have fixed the RTL to fix the name of the net (or the OR gate), but I have yet to do this...


    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • archive
    archive over 19 years ago

    Hi Mike,

    The tricky thing is that the output of the OR gate is both clock and data.

    One experienced AE advice me that the way to handle this is to use "setExcludeNet" command. I think the command is a good workaround. However, I am not using it now as the OR gate is a synthesized gate, and thus the net name will change with every new synthesized netlist. I should have fixed the RTL to fix the name of the net (or the OR gate), but I have yet to do this...


    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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