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clock gating paths

maven7783

Hi All,

In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware.

Can someone suggest some techniques for these kind of violations. 

Parents
  • Hi Bob,All,
    I am seeing a classic reverse case of above, in my design.

    No buffers are being added after ICG cells, and the ICG cell output is going to almost 500 flops directly resulting in huge skew and insertion delays.

    Can someone let me know what might be happening -- I looked at my trace file, and there are only exclude or leaf pins, I dont see any through pins, at all.
    Thanks,
    Rajesh.
Reply
  • Hi Bob,All,
    I am seeing a classic reverse case of above, in my design.

    No buffers are being added after ICG cells, and the ICG cell output is going to almost 500 flops directly resulting in huge skew and insertion delays.

    Can someone let me know what might be happening -- I looked at my trace file, and there are only exclude or leaf pins, I dont see any through pins, at all.
    Thanks,
    Rajesh.
Children
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