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clock gating paths

maven7783

Hi All,

In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware.

Can someone suggest some techniques for these kind of violations. 

Parents

  • Thanks Bob.

    Actually i am using SOC71 so i dont find  setOptMode -clkGateAware option.

    In my design i have made the nets after the icg till the branching point to registers as dontTouchNet, hence the buffers which were in that net got place in capture path of icg clock pin.So my logic got extra time and slack is met.

    But this did not work for all paths.

    I feel while building CTS tool should balance skew even with respect to the clock pin of icg which will reduce violations in clock gating paths .

Reply

  • Thanks Bob.

    Actually i am using SOC71 so i dont find  setOptMode -clkGateAware option.

    In my design i have made the nets after the icg till the branching point to registers as dontTouchNet, hence the buffers which were in that net got place in capture path of icg clock pin.So my logic got extra time and slack is met.

    But this did not work for all paths.

    I feel while building CTS tool should balance skew even with respect to the clock pin of icg which will reduce violations in clock gating paths .

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