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clock gating paths

maven7783

Hi All,

In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware.

Can someone suggest some techniques for these kind of violations. 

Parents

  • Hi Bob,

    i attached a doc which shows rough scenario in my design.

    While building CTS i made the net (shown in brown in the doc)  as dontTouch (in .ctstch file) so that tool while building CTS moved the buffer on the brown line and added it before the clk pin of icg (indicated by blue line in doc) satisfying the latency.

    This is not the scenario of all icgs there were some icgs whose fanout is more than 10.

    Obviously many path will get violated if i specify icg ck pin as leaf port.Tool should not stop at icg ck pin but it should consider the icg ck as intermediate balancing point and not put many buffers after it to meet max delay constraint. 

    i thought of cloning and come back to you after using it. 

     

    Thanks,

    maven. 

    clkgating.doc
Reply

  • Hi Bob,

    i attached a doc which shows rough scenario in my design.

    While building CTS i made the net (shown in brown in the doc)  as dontTouch (in .ctstch file) so that tool while building CTS moved the buffer on the brown line and added it before the clk pin of icg (indicated by blue line in doc) satisfying the latency.

    This is not the scenario of all icgs there were some icgs whose fanout is more than 10.

    Obviously many path will get violated if i specify icg ck pin as leaf port.Tool should not stop at icg ck pin but it should consider the icg ck as intermediate balancing point and not put many buffers after it to meet max delay constraint. 

    i thought of cloning and come back to you after using it. 

     

    Thanks,

    maven. 

    clkgating.doc
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