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clock gating paths

Hi All,

In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware.

Can someone suggest some techniques for these kind of violations.

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maven7783 over 16 years ago

Hi Bob,
ICGs in my design doesnt have dontTouch/dontUse properties.
As you said buffers were placed after icg only to minimize insertion delay in some cases and other cases to meet max tran or max cap constraints.

thanks,
maven.
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maven7783 over 16 years ago

Hi Bob,
ICGs in my design doesnt have dontTouch/dontUse properties.
As you said buffers were placed after icg only to minimize insertion delay in some cases and other cases to meet max tran or max cap constraints.

thanks,
maven.
Cancel
Vote Up 0 Vote Down

Cancel

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