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clock gating paths

maven7783

Hi All,

In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware.

Can someone suggest some techniques for these kind of violations. 

Parents

  •  Hi Bob,

    I have used the script userSetClkLatToIcgCkPins.tcl in my design but could not understand it completely.

    From my understanding, along with the script WNS (after CTS value) was given.

    An sdc output had come having set_clock_latency values equal to WNS ( -1 was given by me) . It indicates clock is made to reach the ck pins of icgs at the earliest time in perCTS stage (this can be confirmed from the reports where other end arrival time is -1), optDesign -preCTS was run and there is no significant improvement.

    Is my understanding correct?

    This script is meant to optimize the data path for the earliest arrival of clock. 

    Thanks,

    Maven. 

Reply

  •  Hi Bob,

    I have used the script userSetClkLatToIcgCkPins.tcl in my design but could not understand it completely.

    From my understanding, along with the script WNS (after CTS value) was given.

    An sdc output had come having set_clock_latency values equal to WNS ( -1 was given by me) . It indicates clock is made to reach the ck pins of icgs at the earliest time in perCTS stage (this can be confirmed from the reports where other end arrival time is -1), optDesign -preCTS was run and there is no significant improvement.

    Is my understanding correct?

    This script is meant to optimize the data path for the earliest arrival of clock. 

    Thanks,

    Maven. 

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