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clock gating paths

maven7783

Hi All,

In my design i got many clock gating setup violations which are due to negative skew i.e., my launch clock delay is more than capture clock delays.Placement in the design is clock gate aware.

Can someone suggest some techniques for these kind of violations. 

Parents

  • Hi maven,

    Thanks for posting this follow-up! I'm glad to hear you've achieved timing closure.

    Your success was due in large part to your dilligence in troubleshooting and addressing the problem.  Thanks for posing the question and engaging in this dialog in the forums- I hope others might benefit from our discussion. I'd like to highlight this topic in a future blog entry.

    -Bob

Reply

  • Hi maven,

    Thanks for posting this follow-up! I'm glad to hear you've achieved timing closure.

    Your success was due in large part to your dilligence in troubleshooting and addressing the problem.  Thanks for posing the question and engaging in this dialog in the forums- I hope others might benefit from our discussion. I'd like to highlight this topic in a future blog entry.

    -Bob

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