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Power/Ground Ports

naderi

Hello eveyone,

If I use SRoute and then NanoRoute, vdd and gnd nets are not connected to the vdd and gnd pads.

In the same flow (I mean the same design, PADs, conf file and global connections), WRoute can connect the vdd and gnd nets to the right pads, only if "Global and Final Route" mode is selected.

Could someone please tell me what different is between WRoute and NanoRoute, and Why NanoRoute cannot connect the nets to the power pads?

I am using STM CMOS90nm technology in Encounter v6.1. My Power pads come with a single inout DUMMY pin. Is there any experience with these pads?

Also, checkdesign shows: "Number of Power/Ground Ports" is 0. How could I define the "Power/Ground Ports"?

 

Thanks,

Ali

 

Parents
  • naderi

     Hi Kari,

    Yes, the core-facing pwr/gnd pins on the power pads, which should supply a core ring. Like what you said, globalNetConnect also warns me that the DUMMY pin is a IO pin (which means it is not pgpin) and it should be of CORE class. However, in the LEF file, its class is defined as PAD and there is no USE POWER/GROUND for the DUMMY pin in its macro.

    Therefore, I cracked the LEF file and added the USE POWER/GROUND for DUMMY pin of VDD/GND pad. But SRoute still couldn't route DUMMY to vdd/gnd nets, and showing some warnings like following:

    **WARN: (SOCDC-348):    The output pin ioco_vssioco_1/DUMMY is connected to power/ground net gnd. This can compromise the delay calculation. Fix the netlist and re-run.

    **WARN: (SOCSR-1256):   Net gnd does not have pad pins to be routed. Please check net list or port class. (must be CORE class).

    Then, I changed the "CLASS PAD;" to "CLASS CORE;" in the LEF file, which didn't help. This time the VDD/GND PADs were placed in the core area and not at the sides, and getting the same warnings.

    I have to mention that my pads' connections are declared in the input synthesized verilog file.

    How should I define the CORE class, and USE POWER/GROUND?

     

    Thanks,

    Ali

Reply
  • naderi

     Hi Kari,

    Yes, the core-facing pwr/gnd pins on the power pads, which should supply a core ring. Like what you said, globalNetConnect also warns me that the DUMMY pin is a IO pin (which means it is not pgpin) and it should be of CORE class. However, in the LEF file, its class is defined as PAD and there is no USE POWER/GROUND for the DUMMY pin in its macro.

    Therefore, I cracked the LEF file and added the USE POWER/GROUND for DUMMY pin of VDD/GND pad. But SRoute still couldn't route DUMMY to vdd/gnd nets, and showing some warnings like following:

    **WARN: (SOCDC-348):    The output pin ioco_vssioco_1/DUMMY is connected to power/ground net gnd. This can compromise the delay calculation. Fix the netlist and re-run.

    **WARN: (SOCSR-1256):   Net gnd does not have pad pins to be routed. Please check net list or port class. (must be CORE class).

    Then, I changed the "CLASS PAD;" to "CLASS CORE;" in the LEF file, which didn't help. This time the VDD/GND PADs were placed in the core area and not at the sides, and getting the same warnings.

    I have to mention that my pads' connections are declared in the input synthesized verilog file.

    How should I define the CORE class, and USE POWER/GROUND?

     

    Thanks,

    Ali

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