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SOC Encounter Bus Delimiters

temp52411

I am currently using SOC Encounter (6.2) for place and route of a digital IC design that I would like to import into ICFB/Virtuoso (5.1.41) using a GDS(II) Stream.  Unfortunately, Virtuoso uses a bus delimiter of <> such as A<3:0> while SOC Encounter uses [] such as A[3:0].  When I import an HDL file (Verilog or VHDL) into Virtuoso to generate a schematic, all buses use <>.  When I perform place and route using the same HDL file in Encounter, all buses use [].  When I export to GSDII and then import that into Virtuoso layout editor and then perform LVS with Assura (3.17), it complains that the buses do not match (i.e. A<3:0> is not the same as A[3:0].  It appears I can not change Virtuoso's bus delimiters, so I was wondering if it was possible to change Encounter's, such as during the export to GDSII.  If anyone has any idea how to do this, I would be very appreciative.  Thank you.

Parents

  • Sorry, I don't know any command to convert bus [ into bus <> inside SOC. However, I don't have the problem when  I use DEF format instead of GDS (save a DEF file inside SOC and then, from dfII, use File->Import->DEF ...).  The bus format in my DEF file is [, but when I use File->Import->DEF to get the DEF file into Virtuoso, the bus format is automatically changed to <>.

     Also, it should be very easy to have a skill code to convert the bus format inside Virtuoso...

    Tongju

     

Reply

  • Sorry, I don't know any command to convert bus [ into bus <> inside SOC. However, I don't have the problem when  I use DEF format instead of GDS (save a DEF file inside SOC and then, from dfII, use File->Import->DEF ...).  The bus format in my DEF file is [, but when I use File->Import->DEF to get the DEF file into Virtuoso, the bus format is automatically changed to <>.

     Also, it should be very easy to have a skill code to convert the bus format inside Virtuoso...

    Tongju

     

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