DifferenceS between and usage of term,fterm,inst,cell,hinst

 Hello Naadhan,

  Assuming you are familiar with Verilog constructs, I'll explain it as follows.  Assume we have a nand gate called NAND2 connected as follows:

NAND2 U42(.A(net1),.B(net2),.Q(net3));

   In this case, the "U42" (the instantiation of the nand gate) would be considered the "inst", "NAND2" would be considered the "cell".  "terms" and "fterms" are essentiallys "pins" but the difference is whether it is a pin of the "cell" (fterm) or the pin of the "inst" (term).  The 'h' in "hinst" and "hterm" simply means it is hierarchical.  For instance, say we have a top-level design "TOP" and a child "CHILD" connected as follows:

 module TOP (in,out);
 input in;
 output out;
 CHILD child_inst(.cin(in),.cout(out));
 endmodule

 module CHILD(cin,cout);
 input cin;
 output cin;
 ...
 endmodule

In this case, 'child_inst' would be an 'hinst' and 'child_inst/cin' would be an 'hterm'.  However, 'CHILD' is still a 'cell' and 'CHILD/cin' and 'CHILD/cout' are still 'fterms'.  Also note the 'TOP' is a cell and 'TOP/in' and 'TOP/out' are 'fterms'.

Does that make sense?

JG

Thank you so much Mr.JG......this  very clear n Crisp and illustraion is so clear. Thanks a lot :-)

 Glad to help!

JG

Just good explanation!

Help to make my concept clearly!

Thank you!