Stats

  • Locked Locked
  • Replies 6
  • Subscribers 90
  • Views 7621
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Stack via on spare gates' pins

archive

Hi layout-ers!

Need your advise on implementing an requirement for spare gate.

I need to put some spare gates in the design; I can do this, and place it well.

However, there is a requirement that the pins of the spare gates (input and output) should have a stacked via on top of its an all the way to the top metal. This is to increase the chance of changing less metal layers when eco is using the spare gates.

So, I need to

1. Do not place the spare gate under power stripes (if not the stacked via will short to the power (input pins are connected to tie-high/tie-low)
2. find a way to add the stacked via on the pins (and even better the gloabl router is able to optimise the routing for congestion with the existance of these stacked via)

One easier way is to create standard cell with those pins; but unfortantely  the standard cell library I am using does not have these features, and I do not wish to create new cells with the stacked pins...

Anyone done this before and know the correct way to do this in SOC? Thanks.

Regards,
Eng Han


Originally posted in cdnusers.org by EngHan
Parents
  • archive

    Hi Li Siang,

    I have to admit that I have not done ECO using spare gate before! All my ECO experience has to deal with re-wiring the non-spare cell. I usually prefer to do the eco routing by hand to assure me that minimum changes to the routing, but I am also observed that auto-ECO routing can do a very good job in preserving existing routing.

    Usually 2 routing layers (at metal3 or above) and 1 (or 2) via layers are sufficient for simple eco routing. If spare cell is just tie high/low and output is unconnected, then we will need to change metal 1/via12/metal2/vial23 also, which make the eco costly. So from this aspect, if we have stack via on spare gate, eco with spare gate can make with less metal layers.

    The idea of stack via on spare gate is quite well-known in serveral companies; they have special standard cell that have this stack via build in (a workaround as most P&R tool I know does not support this requirement). However, a few years ago most P&R tools have problem using those cell as the tool "cannot detect that the standard cell short with the power stripes".

    A special version of this stack via requirement is some special FF has a "probe point" to allow for wafer level probing.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Reply
  • archive

    Hi Li Siang,

    I have to admit that I have not done ECO using spare gate before! All my ECO experience has to deal with re-wiring the non-spare cell. I usually prefer to do the eco routing by hand to assure me that minimum changes to the routing, but I am also observed that auto-ECO routing can do a very good job in preserving existing routing.

    Usually 2 routing layers (at metal3 or above) and 1 (or 2) via layers are sufficient for simple eco routing. If spare cell is just tie high/low and output is unconnected, then we will need to change metal 1/via12/metal2/vial23 also, which make the eco costly. So from this aspect, if we have stack via on spare gate, eco with spare gate can make with less metal layers.

    The idea of stack via on spare gate is quite well-known in serveral companies; they have special standard cell that have this stack via build in (a workaround as most P&R tool I know does not support this requirement). However, a few years ago most P&R tools have problem using those cell as the tool "cannot detect that the standard cell short with the power stripes".

    A special version of this stack via requirement is some special FF has a "probe point" to allow for wafer level probing.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.