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Synthesizing Asynchronous design using RTL compiler

Is it possible to synthesize completely asynchronous design using RTL compiler? If yes, pls provide pointer to related documents or tips on challenges in doing so. Thanks in advance.

grasshopper over 16 years ago

Hi Diablo,
RTL Compiler ultimately does not know what the application of the circuit being synthesized is hence the circuit can indeed be synthesized. In fact, I've seen commercial async tools use RC for synthesis. That being said, glitches are one of the achielles heels of async design and none of the commercial synethsis tools that I am aware of gurantee glitch-free logic. As a result, most async flows address glitch prevention other ways or thought post-processing tools.
hope this helps,
gh-
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grasshopper over 16 years ago

BTW, please post synthesis questions in logic design forum. This forum is mostly intended for EDIS / Velocity questions
gh-
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diablo over 16 years ago

Thanks for the information -gh.
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