Stats

Locked Locked
Replies 8
Subscribers 90
Views 16589
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SOC timing problem

Hi all,

I've a post-P&R timing problem using SOC Encounter.
As you can see in the attached file,
my circuit generates an inverted clock.

The timing analyzer reports a setup-violation between
two FFs which use the inverted and the positive clock.

I've read the reports and I've found that
the combinational delay MAX_DELAY is less than the clock period.
The problem is that the analyzer doesn't identify the correct clock edges
for setup checking.
In particular it should consider the next edge
of CLK_END for a correct check.

In order to eliminate the false violation, I've tried to declare
CLK_NEG as a generated clock in the sdc constraint file:

create_generated_clock -name CLK_NEG -source CLK -invert [get_pins "MODULE_PATH"/MYMOD/INV/Z]

But I get the folloving warning messages:

>Skipped invalid point "MODULE_PATH"/MYMOD/INV/Z
>Empty pin list in get_pins command
>Unsupported commad "create_generated_clock"

I've the following questions:

1. The "create_generated_command" could actually avoid the false violation?

2. If So, can it be applied in a hierarchycal module?

3) What is the correct syntax?

Sorry for the long post,
thank you.

Originally posted in cdnusers.org by giohdl

Parents

archive over 18 years ago

Hello Friend !!

A1. Yes
A2. YES
A3. a sample for your ready reference
create_generated_clock -name CLK_NEG -source [get_pins \
{SYSX/SYSY/friend/CLKROOT/A} \
-divide_by 1 -invert -add -master_clock [get_clocks {CLK}] [get_pins \
{SYSX/SYSY/friend/CLKROOT/Z}

some use-full information about "create_generated_clock" options.
+---+---+---+---+---+-------------------------+
|BG |FE |CTE|RC |CCD| SYNOPSYS |
+---+---+---+---+---+-------------------------+
| Y | Y | Y | Y | Y | create_generated_clock
| Y | Y | Y | Y | Y | [-name clock_name]
| Y | Y | Y | Y | Y | -source master_port_pin
| Y | Y | Y | Y | Y | [-divide_by factor |
| Y | Y | Y | Y | Y | -multiply_by factor]
| Y | Y | Y | Y | Y | [-duty_cycle percent]
| Y | Y | Y | Y | Y | [-invert]
| Y*| Y*| Y*| Y*| Y | [-edges edge_list]
| Y*| Y*| Y*| Y*| Y | [-edge_shift shift_list]
| Y | Y | Y | Y | Y | [-add] (SDC 1.4)
| Y | Y | Y | Y | Y | [-master_clock clock] (SDC 1.4)
| - | - | - | Y | - | [-domain domain_name] (Non-SDC, Non-Synopsys)
| - | - | - | Y | - | [-mode mode_name] (Non-SDC, Non-Synopsys)
|---|---|---|---|---| object_list :
| Y | - | Y?| Y | Y | hierarchical pins
| Y | - | Y | Y | Y | ports
| Y | Y | Y | Y | Y | pins
+---+---+---+---+---+-------------------------+
* FE/BG/RC/CTE UNSUPPORTED :number of edge > 3

NOTE :
=========================================
Key
=========================================
Y : Supported
- : Not supported
? : Unclear, requesting R+D feedback
/ : Not applicable (FE-CTE is timing analysis only)

=========================================
Software Version Info
=========================================
BG : 5.0.14 Ambit BuildGates
FE : 05.20-e093_1 First Encounter (FE-STA)
CTE : 05.20-e093_1 CTE in FE
RC : 05.20-s012_1 RTL-Compiler
CCD : 1.0 USR1 Conformal Constraint Designer
SYNOPSYS : SDC 1.5 Synopsys PT/DC

With Regards,
Mohan Kumar Ch

Originally posted in cdnusers.org by mohanch007
Cancel
Vote Up 0 Vote Down

Cancel

Reply

archive over 18 years ago

Hello Friend !!

A1. Yes
A2. YES
A3. a sample for your ready reference
create_generated_clock -name CLK_NEG -source [get_pins \
{SYSX/SYSY/friend/CLKROOT/A} \
-divide_by 1 -invert -add -master_clock [get_clocks {CLK}] [get_pins \
{SYSX/SYSY/friend/CLKROOT/Z}

some use-full information about "create_generated_clock" options.
+---+---+---+---+---+-------------------------+
|BG |FE |CTE|RC |CCD| SYNOPSYS |
+---+---+---+---+---+-------------------------+
| Y | Y | Y | Y | Y | create_generated_clock
| Y | Y | Y | Y | Y | [-name clock_name]
| Y | Y | Y | Y | Y | -source master_port_pin
| Y | Y | Y | Y | Y | [-divide_by factor |
| Y | Y | Y | Y | Y | -multiply_by factor]
| Y | Y | Y | Y | Y | [-duty_cycle percent]
| Y | Y | Y | Y | Y | [-invert]
| Y*| Y*| Y*| Y*| Y | [-edges edge_list]
| Y*| Y*| Y*| Y*| Y | [-edge_shift shift_list]
| Y | Y | Y | Y | Y | [-add] (SDC 1.4)
| Y | Y | Y | Y | Y | [-master_clock clock] (SDC 1.4)
| - | - | - | Y | - | [-domain domain_name] (Non-SDC, Non-Synopsys)
| - | - | - | Y | - | [-mode mode_name] (Non-SDC, Non-Synopsys)
|---|---|---|---|---| object_list :
| Y | - | Y?| Y | Y | hierarchical pins
| Y | - | Y | Y | Y | ports
| Y | Y | Y | Y | Y | pins
+---+---+---+---+---+-------------------------+
* FE/BG/RC/CTE UNSUPPORTED :number of edge > 3

NOTE :
=========================================
Key
=========================================
Y : Supported
- : Not supported
? : Unclear, requesting R+D feedback
/ : Not applicable (FE-CTE is timing analysis only)

=========================================
Software Version Info
=========================================
BG : 5.0.14 Ambit BuildGates
FE : 05.20-e093_1 First Encounter (FE-STA)
CTE : 05.20-e093_1 CTE in FE
RC : 05.20-s012_1 RTL-Compiler
CCD : 1.0 USR1 Conformal Constraint Designer
SYNOPSYS : SDC 1.5 Synopsys PT/DC

With Regards,
Mohan Kumar Ch

Originally posted in cdnusers.org by mohanch007
Cancel
Vote Up 0 Vote Down

Cancel

Children

No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.