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SOC timing problem

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Hi all,


I've a post-P&R timing problem using SOC Encounter.
As you can see in the attached file,
my circuit generates an inverted clock.


 
The timing analyzer reports a setup-violation between
two FFs which use the inverted and the positive clock.
 
I've read the reports and I've found that
the combinational delay  MAX_DELAY is less than the clock  period.
The problem is that the analyzer doesn't identify the correct clock edges
for setup checking.
In particular it should consider the next edge
of  CLK_END for a correct check.



In order to eliminate the false violation, I've tried to declare
CLK_NEG as a generated clock in the sdc constraint file:

create_generated_clock  -name CLK_NEG -source CLK -invert [get_pins "MODULE_PATH"/MYMOD/INV/Z]

But I get the folloving warning messages:

 >Skipped invalid point "MODULE_PATH"/MYMOD/INV/Z
 >Empty pin list in get_pins command
 >Unsupported commad  "create_generated_clock"
 
 
 I've the following questions:
 
 1. The "create_generated_command" could actually avoid the false violation?
 
 2. If So, can it be applied in a hierarchycal module?
 
 3) What is the correct syntax?
 
 
 Sorry for the long post,
 thank you.


Originally posted in cdnusers.org by giohdl
Parents

  • Hi giohdl,

    While what you are doing can work, I think which edge the tool will use depend on how you define the clock in the first place. The tool will always use the "ideal" clock (i.e. the clock you defined) to determine the clock edge.

    It will be clearer for us if you show us how the clocks are defined.

    In this case, I think re-define the clocks source might work better (in the sense that it is closer to the specification). If the clock source is okay, then I think this path is then a multi-cycle path (becareful. You are capturing a value when it is not stable; potential meta-stable problem here).

    Also, note that "set_max_delay" take into the consideration of clock skew; this is the defination in the SDC.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Reply

  • Hi giohdl,

    While what you are doing can work, I think which edge the tool will use depend on how you define the clock in the first place. The tool will always use the "ideal" clock (i.e. the clock you defined) to determine the clock edge.

    It will be clearer for us if you show us how the clocks are defined.

    In this case, I think re-define the clocks source might work better (in the sense that it is closer to the specification). If the clock source is okay, then I think this path is then a multi-cycle path (becareful. You are capturing a value when it is not stable; potential meta-stable problem here).

    Also, note that "set_max_delay" take into the consideration of clock skew; this is the defination in the SDC.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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