Stats

  • Locked Locked
  • Replies 8
  • Subscribers 90
  • Views 16584
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

SOC timing problem

archive

Hi all,


I've a post-P&R timing problem using SOC Encounter.
As you can see in the attached file,
my circuit generates an inverted clock.


 
The timing analyzer reports a setup-violation between
two FFs which use the inverted and the positive clock.
 
I've read the reports and I've found that
the combinational delay  MAX_DELAY is less than the clock  period.
The problem is that the analyzer doesn't identify the correct clock edges
for setup checking.
In particular it should consider the next edge
of  CLK_END for a correct check.



In order to eliminate the false violation, I've tried to declare
CLK_NEG as a generated clock in the sdc constraint file:

create_generated_clock  -name CLK_NEG -source CLK -invert [get_pins "MODULE_PATH"/MYMOD/INV/Z]

But I get the folloving warning messages:

 >Skipped invalid point "MODULE_PATH"/MYMOD/INV/Z
 >Empty pin list in get_pins command
 >Unsupported commad  "create_generated_clock"
 
 
 I've the following questions:
 
 1. The "create_generated_command" could actually avoid the false violation?
 
 2. If So, can it be applied in a hierarchycal module?
 
 3) What is the correct syntax?
 
 
 Sorry for the long post,
 thank you.


Originally posted in cdnusers.org by giohdl
Parents

  • Dear Giohdl,
    Delighted seeing your explanation.
    In general in system mode all the critical paths are synchronous in nature (only rising edge-triggered )
    Aside please let me add my comments on CTS constraints file. (design.ctstch)
    Things to be considered
    1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
    2. Ideal CLK MaxDelay (setup) and MinDelay (hold) (set_clock_latency).
    3. handling generated clock in CTS by hierarchically CTS ( preserve pin)
    4. Skew alignment for Rising Sync Pins and Falling Sync Pins

    Out of the above 4 topics I will help you in 1 and 3 which are the two different approaches.
    1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
    ClkGroup
    + clockRootPinName
    + clockRootPinName
    You can use the ClkGroup section to balance clock skew between two or more clock trees.

    Alternatively, you can balance skew as follows:
      * run CTS once
     * specify MinDelay constraints for all clock trees with the largest clock phase delay, and
     * rerun CTS. However, using ClkGroup often provides better results.
     It is recommended to use ClkGroup with MinDelay 0 if you need to balance clock skew among multiple clock trees.

    • Clock Tree Specification File Example

    ##------- RouteType
    RouteTypeName double_space
    TopPreferredLayer 7
    BottomPreferredLayer 5
    PreferredExtraSpace 1
    NonDefaultRule double_width
    End

    ##------ Clock Group (Balance skew between two clock trees)
    ClkGroup
    + CLKROOT1/Z
    + CLKROOT2/Z
    ##------ CLK1 -------
    AutoCTSRootPin CLKROOT1/Z
    MaxSkew 300ps
    MinDelay 0.000ns
    MaxDelay 10.000ns
    SinkMaxTran 500ps
    BufMaxTran 500ps
    MaxFanout 32
    addDriverCell BFX8
    LeafPin
    PreservePin
    + BLOCK1/MODULE4/CELL4/Z
    End

    • method 2

             Preserves the net-list after the specified pin.
              FE-CTS builds other portions of a clock tree in such a manner as to balance clock skew with
             the  preserved logic.
              See Figure for Ex. of PreservePin


    Originally posted in cdnusers.org by mohanch007
Reply

  • Dear Giohdl,
    Delighted seeing your explanation.
    In general in system mode all the critical paths are synchronous in nature (only rising edge-triggered )
    Aside please let me add my comments on CTS constraints file. (design.ctstch)
    Things to be considered
    1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
    2. Ideal CLK MaxDelay (setup) and MinDelay (hold) (set_clock_latency).
    3. handling generated clock in CTS by hierarchically CTS ( preserve pin)
    4. Skew alignment for Rising Sync Pins and Falling Sync Pins

    Out of the above 4 topics I will help you in 1 and 3 which are the two different approaches.
    1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
    ClkGroup
    + clockRootPinName
    + clockRootPinName
    You can use the ClkGroup section to balance clock skew between two or more clock trees.

    Alternatively, you can balance skew as follows:
      * run CTS once
     * specify MinDelay constraints for all clock trees with the largest clock phase delay, and
     * rerun CTS. However, using ClkGroup often provides better results.
     It is recommended to use ClkGroup with MinDelay 0 if you need to balance clock skew among multiple clock trees.

    • Clock Tree Specification File Example

    ##------- RouteType
    RouteTypeName double_space
    TopPreferredLayer 7
    BottomPreferredLayer 5
    PreferredExtraSpace 1
    NonDefaultRule double_width
    End

    ##------ Clock Group (Balance skew between two clock trees)
    ClkGroup
    + CLKROOT1/Z
    + CLKROOT2/Z
    ##------ CLK1 -------
    AutoCTSRootPin CLKROOT1/Z
    MaxSkew 300ps
    MinDelay 0.000ns
    MaxDelay 10.000ns
    SinkMaxTran 500ps
    BufMaxTran 500ps
    MaxFanout 32
    addDriverCell BFX8
    LeafPin
    PreservePin
    + BLOCK1/MODULE4/CELL4/Z
    End

    • method 2

             Preserves the net-list after the specified pin.
              FE-CTS builds other portions of a clock tree in such a manner as to balance clock skew with
             the  preserved logic.
              See Figure for Ex. of PreservePin


    Originally posted in cdnusers.org by mohanch007
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.