SOC timing problem

Hi all,


I've a post-P&R timing problem using SOC Encounter.
As you can see in the attached file,
my circuit generates an inverted clock.


 
The timing analyzer reports a setup-violation between
two FFs which use the inverted and the positive clock.
 
I've read the reports and I've found that
the combinational delay  MAX_DELAY is less than the clock  period.
The problem is that the analyzer doesn't identify the correct clock edges
for setup checking.
In particular it should consider the next edge
of  CLK_END for a correct check.



In order to eliminate the false violation, I've tried to declare
CLK_NEG as a generated clock in the sdc constraint file:

create_generated_clock  -name CLK_NEG -source CLK -invert [get_pins "MODULE_PATH"/MYMOD/INV/Z]

But I get the folloving warning messages:

 >Skipped invalid point "MODULE_PATH"/MYMOD/INV/Z
 >Empty pin list in get_pins command
 >Unsupported commad  "create_generated_clock"
 
 
 I've the following questions:
 
 1. The "create_generated_command" could actually avoid the false violation?
 
 2. If So, can it be applied in a hierarchycal module?
 
 3) What is the correct syntax?
 
 
 Sorry for the long post,
 thank you.