Stats

  • Locked Locked
  • Replies 2
  • Subscribers 93
  • Views 13133
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

CTS in nanometer design

ellisyu

Is there any critical guideline for CTS(clock tree synthesis) in 65/45 nm design?

Wider width? Shielding?

Thank you!!

  • Some of the factors to consider include: NDR rules from fab vendor (usually in tech file) Coarseness of the power-grid Availability of routing tracks Congestion with single-shielding vs. double-shielding vs. wide-wires vs. double-wide spacing Availability of balanced buffers/inverters Flavors of high drive-strength balanced buffers/inverters Via-generation requirements (single-via vs. double-via vs. via-array) based on the type of clock-routing Capability to consistently add special via-arrays for clock routes ...among other things

  •  double width and double space for clock nets are enough. Just make sure the clock tree has reasonable level and insertion delay. 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.