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Merging two designs

Shankar P

 I have two digital modules that have been synthesized and placed and routed. Now I want to join them in SoC encounter, do timing analysis and write out the netlist file. 

 I can rewrite a topmodule verilog file calling the individual designs, resynthesize and reroute. Is there someway to avoid that. Please throw me some light on where to start.

Thanks

Shankar

Parents

  •  You could write a top module that calls these two modules as instances (like a hard macro). But then timing could be difficult, because you would need a .lib for each of your pre-existing modules, as well as constraints written that way, and I'm thinking you would rather time flat.

    So, you could still write your top module that includes the two pre-existing modules, make them partitions as if you're doing a top-down hierarchical flow, but you already have the "blocks" built. So you know the size, pin locations, etc. Then you can run assembleDesign (once you have all the data in the right place) which will flatten your completed blocks with your top-level. Then you can run your flat timing and output a flat netlist. It's kind of using the top-down flow backwards, but I think it will work.

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  •  You could write a top module that calls these two modules as instances (like a hard macro). But then timing could be difficult, because you would need a .lib for each of your pre-existing modules, as well as constraints written that way, and I'm thinking you would rather time flat.

    So, you could still write your top module that includes the two pre-existing modules, make them partitions as if you're doing a top-down hierarchical flow, but you already have the "blocks" built. So you know the size, pin locations, etc. Then you can run assembleDesign (once you have all the data in the right place) which will flatten your completed blocks with your top-level. Then you can run your flat timing and output a flat netlist. It's kind of using the top-down flow backwards, but I think it will work.

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