Why do we go for virtual clocks??

Hi Naadhan,

not all designs need virtual clocks but, more often than not, they usually are required to model on-chip to off-chip interactions.

For example, logic driven by a PLL on-chip could have completely different characteristics than the clocked logic it connects to off-chip and we need to model this accurately for the I/O timing to be reasonably accurate.

There are many other applications but usually they involve on / off chip modelling situations but certainly not limited to them

gh-

Thanks a lot grass hopper :-)..... u have mentioned that it is not only limited for modelling io timings....Can you tell me where else this Virtual clocks  be used in the design ...

Thanks&Regards,

NAADHAN

 Hey Naadhan,

 Virtual clocks can also be used within a design to constrain a purely combinational portion of the design. Namely, you create a virtual clock and then set input and output delays on the purely combinational block, with respect to that virtual clock.

Hope this helps,

A.

 Once you have a hierarchical design, you should use virtual clock for your modules after CTS is done.

Hi Alex...thanks ... your point is very clear ;D

Regards
NAADHAN

Hi Franki..."Once we have a hierarchical design ....we should use virtual clock for our models after CTS " ------> can you elaborate it pls? am not clear ...

Thanks & Regards,
NAADHAN

 The postCTS clock are not ideal, and you need to set clock latancy for 'input--> reg' and 'reg--> output' timing path.

You need to set virtual clock to time the IO timing path based on this point.