• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. clock tree quality

Stats

  • Locked Locked
  • Replies 10
  • Subscribers 92
  • Views 17182
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

clock tree quality

Rajesh Vembu
Rajesh Vembu over 16 years ago

What are the metrics (physical and timing-related) that determine if the clock tree built is robust and of good quality?

If i want to compare the clock tree quality built using 2 different clock tree spec files, what would be the steps to follow?

It should be noted that the AutoCTSRootPin definitions in the 2 spec files could be different, hence a one-to-one comparison of the clock tree report (generated using reportClockTree) won't be helpful.

 - Rajesh

  • Cancel
Parents
  • archive
    archive over 16 years ago

     Hi everyone,

    This seems to be an interesting topic! All the metrics you mentioned so far (both of you), are indeed quite important. Usually we are concerned about timing closure and our designs actually being functional that we tend to forget that the clock tree is the major contributor of dynamic power consumption. So, in a design where power consumption is a hard constraint, I would perform IR drop analysis to the two designs and estimate their power consumption using a common VCD file.

     As another experiment, I would run the same test but this time instead of using buffers for the clock tree I would use inverters (generally smaller, faster and less power-hungry than buffers) and see what happens.

     

    -Alex

     

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 16 years ago

     Hi everyone,

    This seems to be an interesting topic! All the metrics you mentioned so far (both of you), are indeed quite important. Usually we are concerned about timing closure and our designs actually being functional that we tend to forget that the clock tree is the major contributor of dynamic power consumption. So, in a design where power consumption is a hard constraint, I would perform IR drop analysis to the two designs and estimate their power consumption using a common VCD file.

     As another experiment, I would run the same test but this time instead of using buffers for the clock tree I would use inverters (generally smaller, faster and less power-hungry than buffers) and see what happens.

     

    -Alex

     

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information