Encounter crashes in netlist import

Hello everyone. I am trying to import a Verilog netlist into SoC Encounter 7.1 but it crashes with a SEGV error when it tries to execute the 'setDrawView' command. Strangely enough, Encounter was running fine one or two days before the problem arised. Installing latest updates for 7.1 and trying with 8.1 too did not have any result. Log file looks like this

@(#)CDS: First Encounter v07.10-s219_1 (32bit) 09/11/2008 21:51 (Linux 2.4)
@(#)CDS: NanoRoute v07.10-s194 NR080828-1515/USR56-UB (database version 2.30, 63.1.1) {superthreading v1.10}
@(#)CDS: CeltIC v07.10-s274_1 (32bit) 09/04/2008 02:57:35 (Linux 2.4.21-37.ELsmp)
@(#)CDS: CTE v07.10-s203_1 (32bit) Sep 10 2008 12:45:53 (Linux 2.4.21-37.ELsmp)
@(#)CDS: CPE v07.13-s009
--- Starting "First Encounter v07.10-s219_1" on Tue Jun 23 13:40:14 (mem=74.1M) ---
--- Running on kalypso.analogies.eu (x86_64 w/Linux 2.6.9-67.ELsmp) ---
This version was compiled on Thu Sep 11 21:51:14 PDT 2008.
Set DBUPerIGU to 1000.
Set Default Mode Capacitance Scale Factor to 1.00
Set Detail Mode Capacitance Scale Factor to 1.00
Set Coupling Capacitance Scale Factor to 1.00
Set Resistance Scale Factor to 1.00
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
<CMD> loadConfig /home/skoutsom/Desktop/Templates/Default.conf 0
Reading config file - /home/skoutsom/Desktop/Templates/Default.conf
<CMD> setUIVar rda_Input ui_timingcon_file netlist/bit_deskew_write_counter_syn.sdc
<CMD> setUIVar rda_Input ui_settop 0
<CMD> setUIVar rda_Input ui_netlist netlist/bit_deskew_write_counter_syn_uniq.v
<CMD> commitConfig
Loading Lef file /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/lef/tcbn90ghp_6lmT2.lef...
Set DBUPerIGU to M2 pitch 280.
Initializing default via types and wire widths ...
**WARN: (SOCLF-200):    Pin 'I' in macro 'ANTENNA' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.

Power Planner/ViaGen version 7.1.45 promoted on 08/20/2008.
viaInitial starts at Tue Jun 23 13:40:56 2009
**WARN: (SOCPP-557):    a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
    VIARULE TURN1 GENERATE
**WARN: (SOCPP-557):    a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
    VIARULE TURN2 GENERATE
**WARN: (SOCPP-557):    a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
    VIARULE TURN3 GENERATE
**WARN: (SOCPP-557):    a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
    VIARULE TURN4 GENERATE
**WARN: (SOCPP-557):    a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
    VIARULE TURN5 GENERATE
**WARN: (SOCPP-557):    a single-layer VIARULE GENERATE for turn-vias is obsolete and is being ignored. You should remove this statement from your LEF file.
    VIARULE TURN6 GENERATE
viaInitial ends at Tue Jun 23 13:40:56 2009
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist 'netlist/bit_deskew_write_counter_syn_uniq.v'

*** Memory Usage v0.134.4.7 (Current mem = 196.297M, initial mem = 74.148M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=196.3M) ***
Top level cell is bit_deskew_write_counter.
Reading max timing library '/PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/timing_power/tcbn90ghpwc.lib' ...
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN2D0' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN2D1' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN2D2' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN2D4' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN2D8' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN2XD1' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN3D0' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN3D1' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN3D2' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN3D4' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN3D8' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN3XD1' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN4D0' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN4D1' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN4D2' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN4D4' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN4D8' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AN4XD1' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AO211D0' is not defined in the library
**WARN: (TECHLIB-436):    Attribute 'max_fanout' on output/inout pin 'Z' of cell 'AO211D1' is not defined in the library
 read 837 cells in library 'tcbn90ghpwc'
Reading min timing library '/PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/timing_power/tcbn90ghpbc.lib' ...
 read 837 cells in library 'tcbn90ghpbc'
Reading max timing library '/PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/timing_power/tcbn90ghptc.lib' ...
 read 837 cells in library 'tcbn90ghptc'
Reading min timing library '/PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/timing_power/tcbn90ghptc.lib' ...
 read 837 cells in library 'tcbn90ghptc'
*** End library_loading (cpu=0.20min, mem=93.2M, fe_cpu=0.28min, fe_mem=289.5M) ***
Starting recursive module instantiation check.
No recursion found.
*****NEW dbFlattenCell is used.
Flattening Cell bit_deskew_write_counter ...
*** Netlist is unique.
** info: there are 3379 modules.
** info: there are 45 stdCell insts.

*** Memory Usage v0.134.4.7 (Current mem = 289.922M, initial mem = 74.148M) ***
CTE reading timing constraint file 'netlist/bit_deskew_write_counter_syn.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
WARNING (CTE-25): Line: 1 of File netlist/bit_deskew_write_counter_syn.sdc : Skipped unsupported command: reset_design


WARNING (CTE-25): Line: 10 of File netlist/bit_deskew_write_counter_syn.sdc : Skipped unsupported command: set_ideal_network


*** Read timing constraints (cpu=0:00:00.1 mem=291.9M) ***
Total number of combinational cells: 520
Total number of sequential cells: 303
Total number of tristate cells: 11
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFFD1 BUFFD0 BUFFD2 BUFFD1P5 BUFFD3 BUFFD2P5 BUFFD4 BUFFD5 BUFFD6 BUFFD8 BUFFD10 BUFFD12 BUFFD16 CKBXD0 CKBXD2 CKBXD1 CKBXD3 CKBXD4 CKBXD6 CKBXD8 CKBXD12 CKBXD16
Total number of usable buffers: 22
List of unusable buffers: BUFFD20 BUFFD24 CKBXD20 CKBXD24 GBUFFD1 GBUFFD3 GBUFFD2 GBUFFD4 GBUFFD8
Total number of unusable buffers: 9
List of usable inverters: CKNXD0 CKNXD1 CKNXD2 CKNXD3 CKNXD4 CKNXD6 CKNXD8 CKNXD12 CKNXD16 INVD1 INVD0 INVD2 INVD1P5 INVD3 INVD2P5 INVD4 INVD5 INVD6 INVD8 INVD10 INVD12 INVD16
Total number of usable inverters: 22
List of unusable inverters: CKNXD20 CKNXD24 GINVD2 GINVD1 GINVD4 GINVD3 GINVD8 INVD20 INVD24
Total number of unusable inverters: 9
List of identified usable delay cells:
Total number of identified usable delay cells: 0
List of identified unusable delay cells: DEL0 DEL005 DEL01 DEL015 DEL1 DEL02 DEL2 DEL3 DEL4
Total number of identified unusable delay cells: 9
All delay cells are dont_use. Buffers will be used to fix hold violations.
*info: set bottom ioPad orient R0
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 10 ps.
Reading Three Cap Table files: -typical /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/encounter/cln90_1p06m_top2_typical.ict.captable -best /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/encounter/cln90_1p06m_top2_rcbest.ict.captable -worst /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/encounter/cln90_1p06m_top2_rcworst.ict.captable ...
**WARN: (SOCEXT-2760):    Layer M7 in the cap table is larger than max number of layers, 6, defined in the LEF file.
**WARN: (SOCEXT-2771):    Top layer, M7,  of Via VIA_6 in the cap table is larger than max number of layers, 6, defined in the LEF file.
**WARN: (SOCEXT-2710):    Cap table for M7 is ignored, the layer is not defined in the design.
**WARN: (SOCEXT-2760):    Layer M7 in the cap table is larger than max number of layers, 6, defined in the LEF file.
**WARN: (SOCEXT-2771):    Top layer, M7,  of Via VIA_6 in the cap table is larger than max number of layers, 6, defined in the LEF file.
**WARN: (SOCEXT-2710):    Cap table for M7 is ignored, the layer is not defined in the design.
**WARN: (SOCEXT-2760):    Layer M7 in the cap table is larger than max number of layers, 6, defined in the LEF file.
**WARN: (SOCEXT-2771):    Top layer, M7,  of Via VIA_6 in the cap table is larger than max number of layers, 6, defined in the LEF file.
**WARN: (SOCEXT-2710):    Cap table for M7 is ignored, the layer is not defined in the design.
Reading EXTENDED_CAP_TABLE section completed.
Three process corner capacitance table is used.
Set cdb_file,max as /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/celtic/tcbn90ghpwc.cdb
Set cdb_file,min as /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/celtic/tcbn90ghpbc.cdb
Set cdb_file as /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/celtic/tcbn90ghptc.cdb
Set qxtech_file as /PDK/TSMC/CRN90G/TCBN90GHP/v150f_v0.1/voltage_storm/tcbn90ghp_6lmT2_lt_dv.cl/icecaps_6_fsg.tch
<CMD> fit
<CMD> setDrawView fplan
Encounter terminated by internal (SEGV) error/signal...


Any help would be appreciated since I've not been able to find a workaround