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How to make nanoroute understand "USEMINSPACING"

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Hi,

I am facing the following issue for quite sometime. Wonder if anyone is also facing the issue and has a solution?

I have "USEMINSPACING OBS OFF ;" in the technolog lef. However, nanoroute places alot of wire at min spacing to "thick blockage". VerifyGeometry is able to detect these DRC, but nanoroute does not detect the violations. It is quite a pain to clean these violations post-layout.

Anyone also face this issue? Thanks.

Regards,
Eng Han



Originally posted in cdnusers.org by EngHan
Parents

  • Hi,

    I look at the remaing violations and observed that they are of the same type.

    The violation is between routed M4 with M4 pin (from the lef). The M4 pin is a power net. When this M4 pin tape to a wide M3 pin (also in the lef), spacing from the VIA34 has to obey wide metal spacig. It look like nanorouter does not understanding this while verifyGeometry detct the error.For now, I am not sure if nanoroute is correct or verifyGeometry is correct.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Reply

  • Hi,

    I look at the remaing violations and observed that they are of the same type.

    The violation is between routed M4 with M4 pin (from the lef). The M4 pin is a power net. When this M4 pin tape to a wide M3 pin (also in the lef), spacing from the VIA34 has to obey wide metal spacig. It look like nanorouter does not understanding this while verifyGeometry detct the error.For now, I am not sure if nanoroute is correct or verifyGeometry is correct.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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