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  3. design without level shifter

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design without level shifter

Layouts
Layouts over 16 years ago
Hi all! In my design one of the block which is Flash/OTP(64 kb) is designed for 1.8v, but my other blocks and core are working at 1.2v and IO voltage is also 1.2v. Is it possible to implement the entire design without level shifter (1.2 - 1.8 ) in between the two blocks communicating with each other(one at 1.2v and other at 1.8v). There is a condition that I cant change the IO voltage(1.2v) and my Flash(1.8v) for my entire design. If possible then what are the ways & how? Will the performance degrade? Thanks in adv. Jitendra
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    admin over 16 years ago

     You must take care when:

        High voltage input are connected to source or drain of pmos transistor in a lower voltage domain. In this case the diode formed by the nwell and substrate will be conducting. So the difference between the voltage domains must have not exceed the diode threshold voltage.

        When the low voltage input is connected to a gate of a pmos in a high voltage domain this transistor may not turn off totally creating a short. You must garantee that the difference between the voltage domains is not upper to threshold of pmos.

    Regards, 

    Julian Pontes

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  • admin
    admin over 16 years ago

     You must take care when:

        High voltage input are connected to source or drain of pmos transistor in a lower voltage domain. In this case the diode formed by the nwell and substrate will be conducting. So the difference between the voltage domains must have not exceed the diode threshold voltage.

        When the low voltage input is connected to a gate of a pmos in a high voltage domain this transistor may not turn off totally creating a short. You must garantee that the difference between the voltage domains is not upper to threshold of pmos.

    Regards, 

    Julian Pontes

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