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  3. Controlling logic names of CTS inserted buffers.

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Controlling logic names of CTS inserted buffers.

archive
archive over 18 years ago

Hello,
I was wondering if there is a way to tailor the instance names of buffers inserted by CTS?  Specifically, what I am trying to do is control where in the logic hierarchy the clock buffers are placed.  I would like any buffers inserted by Encounter to be logically placed inside a specific module in the hierarchy.  This allows for easier import back into the Cadence DFII world after Encounter place and route step.

Anyone had any sucess with this?


Originally posted in cdnusers.org by nph
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  • archive
    archive over 18 years ago

    Hi nph,

    No, there is not a way to alter the CTS naming convention to in an effort to influence where in the logical hierarchy clock buffers get inserted. There probably is a way to do what you're asking about via other mechanisms...

    It sounds like your intent here is controlling the physical and logical hierarchy where clock buffers are inserted. Have you noticed that in some cases, CTS will automatically insert buffers within lower levels of hierarchy? It depends on the netlist and partition structure that CTS is faced with.

    I assume your design has partitions that you'd like to see clock buffers inserted within. You may want to have a look at the "pushdownBuffer" command. This command takes buffers that reside over partitions and pushes them down into the partition- taking care of the netlist and physical changes needed to make this happen.

    It would be helpful to understand more about your design challenge here. Specifically: What is the fanout of the clock trees you're building? Like 5 or 30,000? How many partitions in your design?

    Hope this helps,
    Bob


    Originally posted in cdnusers.org by BobD
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  • archive
    archive over 18 years ago

    Hi nph,

    No, there is not a way to alter the CTS naming convention to in an effort to influence where in the logical hierarchy clock buffers get inserted. There probably is a way to do what you're asking about via other mechanisms...

    It sounds like your intent here is controlling the physical and logical hierarchy where clock buffers are inserted. Have you noticed that in some cases, CTS will automatically insert buffers within lower levels of hierarchy? It depends on the netlist and partition structure that CTS is faced with.

    I assume your design has partitions that you'd like to see clock buffers inserted within. You may want to have a look at the "pushdownBuffer" command. This command takes buffers that reside over partitions and pushes them down into the partition- taking care of the netlist and physical changes needed to make this happen.

    It would be helpful to understand more about your design challenge here. Specifically: What is the fanout of the clock trees you're building? Like 5 or 30,000? How many partitions in your design?

    Hope this helps,
    Bob


    Originally posted in cdnusers.org by BobD
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