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RTL compiler Verilog_out netlist

superman321

Im trying to get a verilog (structural) netlist of a synthesized, mapped design and I would like to have it in "positional" format rather than the deafult named format.

I have tried using the attribute "set_attribute write_vlog_port_association_style positional" which give me an error: 

[TUI-19] The object for this attribute is missing or invalid. [TUI-19] [set_attribute]
        : You must specify a 'instance' object type as the final (fourth) argument when setting the 'write_vlog_port_association_style'  attribute.

Any suggestion on how to use this attribute or any other attribute that may give me a structural "positional" format rather than the default "named" format?

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  • superman321
    gh thanks for the reply!...the error message is exactly abt the object part and i have no idea what i should set it to.. could you elaborate more on the "root level attribute" thanks one again
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  • superman321
    gh thanks for the reply!...the error message is exactly abt the object part and i have no idea what i should set it to.. could you elaborate more on the "root level attribute" thanks one again
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