Mixed signal post-layout simulation flow – spectreVerilog – delay extraction problem

I'm currently working out the mixed-signal simulation flow in cadence. I've found a few documents on the web that helped me smooth out most problems, and used a very simple mixed analog and digital design to test things out (an SPI block with 3 analog inverters on its outputs). I'm having problems generating the sdf file for the mixed_extracted view. I also have two points that I'd like cleared up if possible.

Q1- LVS complains that the gnd! terminal is floating in both schematic and layout, although I did not place any of those in either views. I created a connection in my simulation schematic that wraps over my top-level cell, but not in any component cell.  Although I assume I can ignore this warning, I'm left thinking it might come back at me in an unexpected way. Is it safe to ignore this warning? (next question seems to say no) 

Q2- I separated my analog and digital power nets as VDDA/VSSA and VDD/VSS, respectively. The LVS between schematic and extracted view has no errors (except above mentioned warning). When I run the build mixed-extract dialog, the pearl tools starts running, but declares errors during the "ReadSPF" command, complaining that the digital cells have no ports named VDD or VSS (although they can be seen on the symbols of the mixed-extracted view). As a workaround, I renamed the digital power pins on the top cell to vdd! and gnd!, and the errors disappear. I'm sure there's a better way of doing this, since in the examples I found the instances don't seem to use these global nets directly, only on the top level simulation schematics. Is there a better way to do this?

Main Problem - Interconnect delays generated by pearl are all 0.  With the above changes, pearl manages to generate the sdf file, but only CELL instances have delay values. Every interconnect sections have a 0 delay and/or 0 capacity, with several warning messages:

"Warning: cdc cell delay (sch|I1|q_ShiftRegister_reg\[11\] CKN v -> Q v)
       Ceff too small for cdc algorithm: setting Rs to zero"

After some looking around, I found two possible causes. First, I'm not sure if the tlf files I have contain wire load models. To see if I had an alternative, I went back to the encounter p&r tool to generate the sdf file, and the interconnections had capacitive and delay values that can be used. But this is not quite accurate because it will not take in account the trace lengths outside the digital block, nor the capacitive I/O load of the analog components they hook up with.

Second, the generated spf file that pearl uses has all its capacitance parameters set to 0 pF, which might be understandable for extracts without parasitic capacitor extraction. But shouldn't cadence know the cap values of the gates, just like encounter does? On the other hand, when I use the parasitic_caps extract switch, the built spf file (prior to pearl invocation) has only net definitions, with no instance whatsoever, in which case no sdf file is produced. I also have several warnings concerning the parasitic caps: "*WARNING* MSB: Failed to find the extracted instance name for `+3170` to write do DSPF file."

I'm a bit at a loss as to how to generate the proper delay. I tried to have the simulator generate the delay file, but it only includes the gate delays, not the interconnect delays. Encounter looks to generate the information just fine, but I don't see where or how to do this in Cadence. What should I do to have pearl generate the missing interconnect information from my mixed extract view, without and/or with parasitic capacitors?