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Hard macros power routing issues

dbekiaris

Hello everybody,

 I import a design in SoC Encounter 7.1, where three hard macros (SRAMs) exist. The problem is that when I am trying to create the power stripes and connect them with the core rings to synthesize the power grid, the SRAM p/g pins cannot connect with the remaining power/ground network, although I have selected the proper metal layer from the .lef files of the macros. Is there anything possible to do for this? I tried also to align pins of the specified macros with the power/ground stripes, but it failed again. If it is possible, please help. Thank you very much in advance.

 

Parents

  • Hi dbekiaris,

    whether the problem is for few RAMS or is it for all RAMS. If it is for few RAMS the problem could be orientation of RAM pins. For example ram pins are in MET4 and conventional direction for MET4 is say vertical and RAM is placed in such a way that MET4 pins on RAM are horizontal and when you try to draw stripes over RAM in say MET5. They may not get connected.

    Anyway there is a command to form vias . we can use this command even after the powerplan is completed.

    Before this command select rams on which connection is required. 

    editPowerVia -add_vias 1 -selected_blocks 1 -top_layer MET6 -bottom_layer MET4 -orthogonal_only 1 .

    This is what i understood from problem you described. correct me if i misunderstand the problem and give bit more clarification. 

     

     

     

Reply

  • Hi dbekiaris,

    whether the problem is for few RAMS or is it for all RAMS. If it is for few RAMS the problem could be orientation of RAM pins. For example ram pins are in MET4 and conventional direction for MET4 is say vertical and RAM is placed in such a way that MET4 pins on RAM are horizontal and when you try to draw stripes over RAM in say MET5. They may not get connected.

    Anyway there is a command to form vias . we can use this command even after the powerplan is completed.

    Before this command select rams on which connection is required. 

    editPowerVia -add_vias 1 -selected_blocks 1 -top_layer MET6 -bottom_layer MET4 -orthogonal_only 1 .

    This is what i understood from problem you described. correct me if i misunderstand the problem and give bit more clarification. 

     

     

     

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