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Hard macros power routing issues

dbekiaris

Hello everybody,

 I import a design in SoC Encounter 7.1, where three hard macros (SRAMs) exist. The problem is that when I am trying to create the power stripes and connect them with the core rings to synthesize the power grid, the SRAM p/g pins cannot connect with the remaining power/ground network, although I have selected the proper metal layer from the .lef files of the macros. Is there anything possible to do for this? I tried also to align pins of the specified macros with the power/ground stripes, but it failed again. If it is possible, please help. Thank you very much in advance.

 

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  • dbekiaris
    Hi surajece01 Thank you very much for your helpful and immediate response!However, the problem is that I propable do not need any power vias to be added, as far as the stripes I selected have been put at the metal layer where the VDD/VSS of SRAMS are also placed. So, I suppose there is no need for vias. The problem is that the power grid creation takes a lot of time and the messages during the execution are not that emcouraging (e.g. CPU time for FollowPin 0 seconds). Does this message means problems with the follopin connections ? Thank you very much again in advance. Kind Regards dbekiaris
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  • dbekiaris
    Hi surajece01 Thank you very much for your helpful and immediate response!However, the problem is that I propable do not need any power vias to be added, as far as the stripes I selected have been put at the metal layer where the VDD/VSS of SRAMS are also placed. So, I suppose there is no need for vias. The problem is that the power grid creation takes a lot of time and the messages during the execution are not that emcouraging (e.g. CPU time for FollowPin 0 seconds). Does this message means problems with the follopin connections ? Thank you very much again in advance. Kind Regards dbekiaris
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