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Hard macros power routing issues

dbekiaris

Hello everybody,

 I import a design in SoC Encounter 7.1, where three hard macros (SRAMs) exist. The problem is that when I am trying to create the power stripes and connect them with the core rings to synthesize the power grid, the SRAM p/g pins cannot connect with the remaining power/ground network, although I have selected the proper metal layer from the .lef files of the macros. Is there anything possible to do for this? I tried also to align pins of the specified macros with the power/ground stripes, but it failed again. If it is possible, please help. Thank you very much in advance.

 

Parents

  • I have seen the similar issue, then I debug this way:   I generate a hardmarco with  IO row, power ring and stripe,  

    when I do Sroute for the hardmarco, I createPGpin VDD and VSSI set extend POWER pin to the boundary, then I generate  LEF by lefOut -PGlayer 1,2 

       I debug the LEF, it show VDD and VSS as POWER pin,

       then I load the top level, I see exactly the problem you show here, top level cannot hook up the stripe and ring, there are open on blockwire and follow pin

     

     

Reply

  • I have seen the similar issue, then I debug this way:   I generate a hardmarco with  IO row, power ring and stripe,  

    when I do Sroute for the hardmarco, I createPGpin VDD and VSSI set extend POWER pin to the boundary, then I generate  LEF by lefOut -PGlayer 1,2 

       I debug the LEF, it show VDD and VSS as POWER pin,

       then I load the top level, I see exactly the problem you show here, top level cannot hook up the stripe and ring, there are open on blockwire and follow pin

     

     

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