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Recommend steps using First Encounter

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Hello.
I'm in the process of verifying what are the necessary steps to achieve fully placed & routed design using First Encounter - I've read few tutorials and assembled the following steps:

* Design import (sythesized verilog file, SDC etc.)
* Floorplanning
* Power planning (power rings,power stripes and routing)
* Placement
* Pre-CTS timing optimization
* Clock tree synthesis (creating specification, specifying it and the actual clock tree synthesis)
* Post-CTS timing optimization
* Routing using NanoRoute
* Post-routing timing optimization
* Filling (fillers,metal fills)
* Verifying
* Exporting results

Your input on the validity of those steps and ideas for possible needed changes would be much appreciated.

Thank You,
Adi. 


Originally posted in cdnusers.org by adi_j
Parents

  • For a mixed-signal design where a schematic rather than a Verilog netlist is the starting point, Virtuoso-XL can be used to convert the schematic view to a layout view using a flow involving the V-XL command:  Generate Physical Hierarchy.

    After floorplanning in V-XL, output a DEF file which captures your floorplan.    The LEF views of your IPs along with this DEF file can be imported to First Encounter where you continue in the recommended FE flow.

    HTH ...

Reply

  • For a mixed-signal design where a schematic rather than a Verilog netlist is the starting point, Virtuoso-XL can be used to convert the schematic view to a layout view using a flow involving the V-XL command:  Generate Physical Hierarchy.

    After floorplanning in V-XL, output a DEF file which captures your floorplan.    The LEF views of your IPs along with this DEF file can be imported to First Encounter where you continue in the recommended FE flow.

    HTH ...

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