Stats

  • Locked Locked
  • Replies 1
  • Subscribers 92
  • Views 13908
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Problem with Encounter Library Characterizer

RungBin

While I am running ELC to characterize a NAND gate, I encounter the following problem with HSPICE simulation. I found that there is a line .include '/home/csrlin/elc/LibChar/rf018.l' in my SPICE netlist file. If I replace this line with .LIB '/home/csrlin/elc/LibChar/rf018.l' tt, the error disappears and the problem is solved, where rf108.l is the SPICE library file name ( aslo the SPICE model file). Since the SPICE netlist file is generated and used by db_spice command, I have no control over the generation of SPICE netlist. I am looking forward to your kind help. Thank you very much.

Sincerely,

 Rung-Bin

 The error message, ELC cmmand file, configuration file, and SPICE netlist for AND2 are as follows.

**** Error message from HSPICE simulation ****

Using: /usr/cad/synopsys/hspice/cur/hspice/linux/hspice
 ****** HSPICE - Z-2007.03-SP1 32-BIT (May 25 2007) 09:43:09 08/16/2009 linux
  FLOATING license(s) on SERVER lscic3
 lic:
 Init: read install configuration file: /usr/cad/synopsys/hspice/cur/hspice/meta.cfg
 Init: hspice initialization file: /usr/cad/synopsys/hspice/cur/hspice/hspice.ini
  END

**error** could not find library file named
 tt_rfmos                                  

**** Command file *****

db_open basic_char
db_prepare -f
db_spice -keep_log
db_meas -design AND2X1 -process typical -id D0001 -report DF_0001.rpt
db_output -lib out.lib -process typical -state
db_close
exit

**** Configuration file *****

#Specify the environment variable settings
EC_SIM_USE_LSF=1;
EC_SIM_LSF_CMD=" ";
EC_SIM_LSF_PARALLEL=10;
EC_SPICE_SIMPLIFY=1;
EC_SIM_SUPPLY1_NAMES="VDD";
EC_SIM_SUPPLY0_NAMES="GND";
EC_CHAR="ECSM-TIMING ECSM-POWER";
#EC_SIM_TYPE="spectre";
#EC_SIM_NAME="spectre";
#Specify the characterization inputs.
SUBCKT="AND2X1";
LIB="rf018.l";    // I remove this line and the line below, but the problem remains
CORNER="tt";
MODEL="rf018.l";
DESIGN="AND2X1";
#EXPAND="AND2X1";
SETUP="setup";
PROCESS="typical";       

**** SPICE Netlist ****

* * design : AND2X1 / process : typical / id : D0000 (2009/08/16 09:43:08) * *
.include '/home/csrlin/elc/LibChar/rf018.l'
* * ***************** * *
* * COMPONENT CIRCUIT * *
* * ***************** * *
.include '/home/csrlin/elc/LibChar/basic_char.ipdb/AND2X1.design/simulate/subckt'
* *  *******************  * *
* *  INSTANCE DEFINITION  * *
* *  *******************  * *
X_AND2X1
+ VDD
+ GND
+ Y
+ A
+ B
+ AND2X1
V_VDD VDD 0 DC 1.8
V_GND GND 0 DC 0
V_Y Y Y_ 0
C_Y Y_ 0 0.35F
V_A A 0 PWL( 0  0  37.5P  1.8  0.18U  1.8  )
V_B B 0 DC 1.8
* *  ****************  * *
* *  SIMULATION SETUP  * *
* *  ****************  * *
.TEMP 25
.TRAN 0.1P 0.18U
.IC V(Y)=0
.PROBE TRAN V(VDD)
.PROBE TRAN I(V_VDD)
.PROBE TRAN I(V_VDD)
.PROBE TRAN V(GND)
.PROBE TRAN I(V_GND)
.PROBE TRAN V(Y)
.PROBE TRAN I(V_Y)
.MEASURE TRAN point0 FIND V(Y) WHEN V(Y)=1.791
.PROBE TRAN V(A)
.PROBE TRAN I(V_A)
.MEASURE TRAN point1 FIND V(A) WHEN V(A)=1.791
.PROBE TRAN V(B)
.PROBE TRAN I(V_B)
.measure tran delay trig v(A) val=0.900000 cross=1 targ v(Y) val=0.900000 cross=1
.measure tran slew trig v(Y) val=0.180000 cross=1 targ v(Y) val=1.620000 cross=1
.measure tran input_slew trig v(A) val=0.180000 cross=1 targ v(A) val=1.620000 cross=1
.OPTIONS PROBE POST=1 ALT999
.OPTION AUTOSTOP
.ALTER
V_Y Y Y_ 0
C_Y Y_ 0 21F
                                                                               

  •  Hi Rung-Bin,

              In the configuration file, I see the following three lines :

    LIB="rf018.l";    // I remove this line and the line below, but the problem remains
    CORNER="tt";
    MODEL="rf018.l";

     Can you please do the following? Please see below steps:

    1. Comment out  'LIB="rf018.l"' line, 'CORNER="tt"' line and 'MODEL="rf018.l"' line.

    2. Create a file called "MODEL_FILE". In this file, add the following lines.

     * This first line should be a comment line in the MODEL_FILE we are creating

    simulator lang=spice

    .lib "/home/csrlin/elc/LibChar/rf018.l" tt

    3. Save and close the  "MODEL_FILE".

    4. Now use the following line in the elc configuration file:

         MODEL="MODEL_FILE"

    5. Try re-running elc again with this updated configuration file.

        If the above steps do not resolve the problem, is it possible for you to send the subckt for the cell you are characterizing, setup file and the rf018.l Spice library file?

     

    Regards,

    Deen

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.