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Top Level CTS of a Hierarchical Design

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 Hello everyone,

 Let's say we have a hierarchical design composing of four blocks, each of which is designed by a different person. So the four engineers deliver four GDS files for top level assembly. It's safe to assume that each block will have a different clock latency (the delay from the block's clock input to the actual clock pins of its registers). So, how do you perform top level CTS with these blocks? Because even if you do an H-tree and balance the clock arrival time to the clock pin of every block, you still end up with skew between the registers of different blocks, due to the difference in the clock latency. Is there a tool (maybe VCAR?) that flattens the design and routes the top level clock tree?

 

Many thanks,

A.   

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  •  When you run CTS at the block-level, you should always create a macromodel. (Use the -macromodel switch of clockDesign.) This will create a .ctsmdl file for the block that can be used at the top-level. That way, the top-level sees what the delay is INSIDE each block, and can balance the top-level tree accordingly. I believe you can generate a macromodel for a finished block (so you don't have to go back to the CTS step) with reportClockTree -macromodel.

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  •  When you run CTS at the block-level, you should always create a macromodel. (Use the -macromodel switch of clockDesign.) This will create a .ctsmdl file for the block that can be used at the top-level. That way, the top-level sees what the delay is INSIDE each block, and can balance the top-level tree accordingly. I believe you can generate a macromodel for a finished block (so you don't have to go back to the CTS step) with reportClockTree -macromodel.

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