Stats

  • Locked Locked
  • Replies 2
  • Subscribers 92
  • Views 13026
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

how to calculate the physical size?

learnlearn1

Hi all, I find the following info from osu018_stdcells.lef about Nand2x1gate.

I need the phyiscal size of the gate, so I calcuate in this way:

         2.4*10*lamda^2= 0.776 um^2

But this area seems too small. Any help? thanks!

-----------------------------------------------------------

 MACRO NAND2X1
  CLASS  CORE ;
  FOREIGN NAND2X1 0.000 0.000 ;
  ORIGIN 0.000 0.000 ;
  SIZE 2.400 BY 10.000 ;
  SYMMETRY X Y  ;
  SITE core ;
  PIN A
    DIRECTION INPUT ;
    PORT
      LAYER metal1 ;
        RECT 0.200 2.900 0.600 3.700 ;
    END
  END A
  PIN B
    DIRECTION INPUT ;
    PORT
      LAYER metal1 ;
        RECT 1.800 5.300 2.200 6.100 ;
    END
  END B

  • Hi

    The physical size of a standard cell is given in the lef. You need not multiply it with any factors like lamda.

    But you consider technology or length of gate of transistor , that must be equal to lamda divided by 2, to adapt lamda based design rules.

    Regards,

    VB 

  •  I looks like you truncated the LEF, because the power pins were not included.

    One thing to be aware of is that most libraries have overlapping power rails, so the size in the LEF is actually smaller then the actual extent of the cell layout.  So the area in LEF will be smaller then what the layout tool will think the size of the cell is. The LEF size is usually represented as a boundary in the layout view.

    Since the cells are overlapped, you should use the LEF size when calculating the actually used area.  When calculating area using LEF, it will be slightly smaller by the width of one power rail in Y dimension, because the rails will stick out by 1/2 rail width at the top and the bottom of a cell cluster.

    Regards,

    - Tom Belpasso

    Integrated Vision

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.