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Problem in using v2lvs to convert verilog netlist into spice netlist

huybforever

I use the command:

v2lvs -v lp5_16b.nl.v -o lp5_16.tlnl.sp

But the generated netlist can not be simulated in HSPICE since it has syntax like "$PINS" in the netlist.

I heard that if you want the spice netlist can be simulated using HSPICE, you have to add the "-i" option. So I use:

v2lvs -v lp5_16b.nl.v -o lp5_16.tlnl.sp -i

But it reports error:

Error: no module declaration for module HS65_LS_NAND2AX14 first encountered in module lp5_16b_DW01_add_70
       (-i switch requres Verilog declarations for all modules.)

Who can tell me how to solve this problem?

Should I add the "-l" or "-s" option?

 Thanks a lot! 

 

 

  • BobD

    Could you let us know which Cadence tool v2lvs is from so I can track down someone to field your question?

    Thanks,
    Bob

  • rh0dium
    huybforever,

    First off v2lvs is a product from Mentor. "The V2LVS (Verilog-to-LVS) converter translates a Verilog structural netlist into a LVS SPICE netlist suitable for Calibre nmLVS/nmLVS-H comparison against a layout." Furthermore it does not make it an HSPICE (From Synopsys) simulatable compatible netlist. Specifically the "-i" option you specifies that calls to subcircuits with pins be done in order, according to traditional SPICE rather than with $PINS construct. Make no question about it - what you are trying to do is not going to work. Since you are on a Cadence page why don't you just do a verilog-in then a spice-out.

    HTH.

    Steve

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