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get rid of 'WARN' & 'ERRORS' after design import

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Hi all, I'M using cadence SOC encounter 5.2 with libraries from artisan. After importing my design I get warning & error as: **WARN: (SOCLF-58): Cell 'ANTENNA' has been found in DB so only antenna data will be loaded. Any other data will be skipped. **WARN: Module is not defined in CDUMP/LEF files. It would be treated as an empty module. Reading timing constraint file '.sdc' ... **WARN[line 17]: Skipped invalid point Sclk(clock pin) ERROR: Cannot find 'clocks' that match 'Sclk' (File .constr.1920.pt, Line 9) . ==> ERROR: Can't get clock definition for clock '' (File .constr.1920.pt, Line 9) . Info: read_dc_script finished with 0 WARNING and 2 ERROR . **WARN: Input Transition Time will be transferred from 0ps to 0.1ps inside FE. Please let me know in detail how to remove it. Thanks!


Originally posted in cdnusers.org by vlsi_dude
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