Stats

  • Locked Locked
  • Replies 1
  • Subscribers 90
  • Views 12708
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Declaring analog power

KVBABU

 Hi All,

 

After synthesis,I want to  declare digital power nets in the verilog netlist as supply0 & supply1. and its good and working fine.

But, i want to declare analog powernets also. Could you suggest any other syntax for this. Because, if use the same syntax, i suppose the tool can not differentiate them.

so is there any alternative

Regards,

KVB 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.