Get all register related to ONE clock?

I sorry that there is one typo, In the approach one:
"But I can know which clock this term is connect to " should be "But I can NOT know which clock this term is connect to "

Dear aidans:

Seem that there is a method, it's a makeup to your approach 1.
After 'dbIsTermClk $termPtr ', you can add 'dbTermNet' to get the net connected to this clock pin. Then you can trace through this net (across all the buffers & inverters) to get the root clock net, or get the generated clock net, if the net is your MCLK or ECLK, I think it is OK. But this needs a lot of work.

Yours EminemShow

Yes, we can trace all the clock net in theory, since there are limited clock nets in the database.
But I think this kind of appoach is to difficult to handle more complex clock tree. Is there a smart way to do this ?

In PrimeTime, we can get this register list easily. And now we try to do all the thing inside SOC Encounter, since we our backend team use Encounter flow.

Great question- I'm glad you asked it.

In FE, there's a couple of different ways to probe the db. The long-standing mechanism I call "FE-TCL"- commands like "dbIsTermClk" and "dbForEachClockDomainInst" are FE-TCL commands. They've been around forever and are great for probing things in the physical realm. However, for information that falls in the timing realm there's CTE-TCL (Common Timing Engine-TCL) commands. These are relatively new within the FE environment (within the 6.1/6.2 timeframe), but what's nice about the CTE-TCL commands is that they provide the ability to query timing efficiently. The example task you're asking about here fits better within the CTE-TCL commands. FE-TCL and CTE-TCL commands are all available at the regular encounter prompt- they're complimentary sets of functionality.

So, with a netlist like this:
module testcase (clk1, clk2);
input clk1;
input clk2;
wire net1;
wire net2;
wire net3;
DFFX1 i0(.CK(clk1), .Q(net1));
DFFX1 i1(.CK(clk1), .D(net1));
DFFX1 i2(.CK(clk2), .Q(net2));
DFFX1 i3(.CK(clk2), .D(net2), .Q(net3));
DFFX1 i4(.CK(clk2), .D(net3));
endmodule

...and a SDC like this:
create_clock -period 1 -name clk1 [get_ports clk1]
create_clock -period 1 -name clk2 [get_ports clk2]

You could get the registers associated with each like this:
encounter1> report_timing
encounter 6> all_registers -clock clk1
i0 i1
0x8
encounter 7> all_registers -clock clk2
i2 i3 i4
0x9

Have a look at the "Timing Constraint Commands" section in "fetxtcmdref.pdf" for more information on commands like this.

Let me know what you think of this and whether it would be OK with you to operate with these CTE-TCL commands instead of FE-TCL for probing timing-related information like this.

Hope this helps,
Bob

Thanks Bob, I get the job done by CTE-TCL command. The result I got in SOC E is the same with that from PrimeTime.
One remider is that, In SOC Encounter, all_register -clock CLKNAME command should be used after we build timing graph. (report_timing )