listing all the sinks of a clock

Rounding up the list of sink pins is a bit different depending on whether you're looking for clocks as defined in the timing constraints file -or- CTS clocks.

If you're looking to visualize CTS trees in the GUI you might want to look at the Clock Tree Analyzer and highlight all of the instances in the clock tree (pre or post CTS).  There's also Clock->Display Clock Tree->Display min/max paths if you wanted to get the sink with the largest delay postCTS.

For clocks as defined in the timing constraint file, you could define them as CTS clock roots and examine them with the Clock Tree Analyzer.

If you really wanted to, you could script this up.  Here's a sample procedure that would find all of the registers on a given logical clock and find the one with the largest distance from the source:

set clockName vclk1
set source [get_property [get_clocks vclk1] sources]
set sourceX [get_property $source x_coordinate]
set sourceY [get_property $source y_coordinate]
set furthestDistance 0
foreach_in_collection register [all_registers -clock vclk1] {
  set inst [dbGetInstByName [get_property $register hierarchical_name]]
  set pt [dbGet $inst.pt]
  set x [lindex [lindex $pt 0] 0]
  set y [lindex [lindex $pt 0] 1]
  set dist [expr abs($x - $sourceX) + abs($y - $sourceY)]
  if {$dist > $furthestDistance} {
    set furthestDistance $dist
    set furthestInst $inst
  }
}
selectInst [file dirname [get_property $source hierarchical_name]]
Puts "The source of clock $clockName is [get_property $source hierarchical_name] at $sourceX $sourceY"
Puts "There are [sizeof_collection [all_registers -clock vclk1]] registers connected to this clock"
Puts "The furthest register is [dbGet $furthestInst.name] at [dbGet $furthestInst.pt]"
selectInst [dbGet $furthestInst.name]

When you run it, it would select the source instance and the farthest sink and output text like this:

The source of clock vclk1 is DTMF_INST/TEST_CONTROL_INST/i_150/Y at 775.170 656.040
There are 393 registers connected to this clock
The furthest register is DTMF_INST/TDSP_CORE_INST/EXECUTE_INST/alu_cmd_reg_3 at {395.34 1156.96}

Hope this is helpful,
Bob

thanks a lot Bob

can u tell me how can i make sure that after cts the clock tree is build for all sinks with out any failure?

regards

suresh

The Clock Tree Analyst has functionality that lists FFs not in any clock tree. ie, the FFs in the design that aren't considered sink pins after specifying and tracing the clock trees you've defined in your clock tree spec file.  It is accessible from the Clock->Clock Tree Analyst, and then Tool->List FFs not in Clock Tree...

Hope this helps,
Bob