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Does reset requires a tree structure like clock?

gops
Does reset also require a tree structure like clock? Can anybody please tell under what scenario a design need to have a dedicated reset tree structure should? Also how can I implement reset tree in encounter, can I do it just by writing another ctsch file considering reset as a clock for the purpose?
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  • The difference between the buffer tree that's built by optDesign and CTS is whether the tool attempts to balance the skew between the endpoints.

    For optDesign we want the tool to build a tree that produces the best timing even if the tree isn't balanced.  For example, if we had a sink in a high fanout tree that was more timing critical than the others, we'd want optDesign to build a tree that delivered the signal to the timing critical sink earlier than the other sinks.

    For CTS, we want the tool to create a tree that balances skew between all of the sinks.  This is desirable in a clock tree scenario because we typically want to minimize skew between registers as a starting point (though we may employ useful skew techniques later where we task the tool to intentionally skew certain registers to improve timing).

    For reset trees, I would recommend allowing the tool to use optDesign's build in buffering algorithm as a starting point.  If you see timing violations arise because of a timing constraint that enforces that the bits in a bus arrive within a certain window, then I'd seek to build a balanced tree.  If you need to go that route, I'd recommend using bufferTreeSynthesis instead of faking the tool out building it with ckSynthesis.

    Great question- hope this response helps...

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  • The difference between the buffer tree that's built by optDesign and CTS is whether the tool attempts to balance the skew between the endpoints.

    For optDesign we want the tool to build a tree that produces the best timing even if the tree isn't balanced.  For example, if we had a sink in a high fanout tree that was more timing critical than the others, we'd want optDesign to build a tree that delivered the signal to the timing critical sink earlier than the other sinks.

    For CTS, we want the tool to create a tree that balances skew between all of the sinks.  This is desirable in a clock tree scenario because we typically want to minimize skew between registers as a starting point (though we may employ useful skew techniques later where we task the tool to intentionally skew certain registers to improve timing).

    For reset trees, I would recommend allowing the tool to use optDesign's build in buffering algorithm as a starting point.  If you see timing violations arise because of a timing constraint that enforces that the bits in a bus arrive within a certain window, then I'd seek to build a balanced tree.  If you need to go that route, I'd recommend using bufferTreeSynthesis instead of faking the tool out building it with ckSynthesis.

    Great question- hope this response helps...

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